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1 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c bicmos lvpecl clock generator ? device specification sonet/sdh/atm oc-12 transmitter and receiver S3037 features ? complies with bellcore and itu-t specifications for jitter tolerance, jitter transfer, and jitter generation ? on-chip high-frequency plls for clock generation and clock recovery ? supports 155.52 mbit/s (oc-3) and 622.08 mbit/s (oc-12) ? selectable reference frequencies of 19.44 or 77.76 mhz ? interface to both lvpecl and lvttl logic ? simple interface with 3.3 v or 5 v optical modules ? directly compatible with 3.3 v or 5 v network interface devices ? 8-bit lvttl data path ? compact 10 mm 64 pqfp package ? diagnostic loopback mode ? low jitter lvpecl serial interface ? single 3.3 v supply applications ? sonet/sdh-based transmission systems ? sonet/sdh modules ? sonet/sdh test equipment ? atm over sonet/sdh ? section repeaters ? add drop multiplexers (adm) ? broad-band cross-connects ? fiber optic terminators ? fiber optic test equipment figure 1. system block diagram sonet/sdh/atm oc-3/12 transceiver w/cdr S3037 general description the S3037 sonet/sdh transceiver chip is a fully integrated serialization/deserialization sonet oc-12 (622.08 mbit/s) and oc-3 (155.52 mbit/s) interface de- vice. the chip performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with sonet/sdh transmission standards. the device is suitable for sonet-based atm applications. figure 1 shows a typical network application. on-chip clock synthesis is performed by the high- frequency phase-locked loop on the S3037 transceiver chip allowing the use of a slower external transmit clock reference. clock recovery is performed on the device by synchronizing its on-chip vco di rectly to the incoming data stream. the S3037 also per- forms sonet/sdh frame detection. the chip can be used with a 19.44 or 77.76 mhz reference clock, in support of existing system clocking schemes. the low jitter lvpecl interface guarantees compli- ance with the bit-error rate requirements of the bellcore and itu-t standards. the S3037 is pack- aged in a 10 mm 64 pqfp, offering designers a small package outline. S3037 sonet/sdh transceiver network interface processor network interface processor S3037 sonet/sdh transceiver otx orx otx orx 8 8 8 8
2 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c sonet overview synchronous optical network (sonet) is a stan- dard for connecting one fiber system to another at the optical level. sonet, together with the synchro- nous digital hierarchy (sdh) administered by the itu-t, forms a single international standard for fiber interconnect between telephone networks of differ- ent countries. sonet is capable of accommodating a variety of transmission rates and applications. the sonet standard is a layered protocol with four separate layers defined. these are: ? photonic ? section ? line ? path figure 2 shows the layers and their functions. each of the layers has overhead bandwidth dedicated to administration and maintenance. the photonic layer simply handles the conversion from electrical to opti- cal and back with no overhead. it is responsible for transmitting the electrical signals in optical form over the physical media. the section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. key functions of this layer are framing, scrambling, and error moni- toring. the line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. its main functions are synchronization, multiplexing, and reli- able transport. the path layer is responsible for the actual transport of services at the appropriate signal- ing rates. data rates and signal hierarchy table 1 contains the data rates and signal designa tions of the sonet hierarchy. the lowest level is the basic sonet signal referred to as the synchronous trans port signal level-1 (sts-1). an sts- n signal is made up of n byte-interleaved sts-1 signals. the optical counterpart of each sts- n signal is an optical carrier level- n signal (oc- n ). the S3037 chip supports oc-3 and oc-12 rates (155.52 and 622.08 mbit/s). frame and byte boundary detection the sonet/sdh fundamental frame format for sts-12 consists of 36 transport overhead bytes fol- lowed by synchronous payload envelope (spe) bytes. this pattern of 36 overhead and 1044 spe bytes is repeated nine times in each frame. frame and byte boundaries are detected using the a1 and a2 bytes found in the transport overhead. (see figure 3.) for more details on sonet operations, refer to the bellcore sonet standard document. elec. optical data rate (mbit/s) sts-1 oc-1 51.84 sts-3 stm-1 oc-3 155.52 sts-12 stm-4 oc-12 622.08 sts-24 stm-8 oc-24 1244.16 sts-48 stm-16 oc-48 2488.32 end equipment end equipment payload to spe mapping maintenance, protection, switching optical transmission scrambling, framing fiber cable section layer section layer photonic layer photonic layer line layer line layer path layer path layer layer overhead (embedded ops channel) functions 192 kbps 0 kbps 576 kbps table 1. sonet signal hierarchy figure 2. sonet structure figure 3. stsC12/ocC12 frame format 9 rows 12 a1 bytes 12 a2 bytes a1 a1 a1 a1 a2 a2 a2 a2 transport overhead 36 columns 36 x 9 = 324 bytes synchronous payload envelope 1044 columns 1044 x 9 = 9396 125 sec s s
3 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c characteristics performance the S3037 pll complies with the jitter specifications proposed for sonet/sdh equipment defined by the t1x1.6/91-022 document, when used as specified. jitter transfer jitter transfer function is defined as the ratio of jitter on the output oc-n/sts-n signal to the jitter applied on the input oc-n/sts-n signal versus frequency. jitter transfer requirements are shown in figure 5. the measurement condition is that input sinusoidal jitter up to the mask level in figure 4 be applied for each of the oc-n/sts-n rates. input jitter tolerance input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input sig- nal that causes an equivalent 1 db optical/electrical power penalty. sonet input jitter tolerance require- ments are shown in figure 4. S3037 performance is shown in table 2. jitter generation the jitter of the serial data outputs shall not exceed 0.01 ui rms when a serial data input with less than 14 ps (oc-12) or 56 ps (oc-3) rms jitter is presented to the serial data inputs. S3037 overview the S3037 transceiver implements sonet/sdh se- rialization/deserialization, transmission, and frame detection/recovery functions. the block diagram in figure 6 shows the basic operation of the chip. this chip can be used to implement the front end of sonet equipment, which consists primarily of the serial transmit interface and the serial receive inter- face. the chip handles all the functions of these two elements, including parallel-to-serial and serial-to-par- allel conversion, clock generation and recovery, and system timing. the system timing circuitry consists of management of the data stream, framing, and clock distribution throughout the front end. the S3037 is divided into a transmitter section and a receiver section. the sequence of operations is as follows: transmitter operations: 1. 8-bit parallel input 2. parallel-to-serial conversion 3. serial output receiver operations: 1. clock and data recovery from serial input 2. frame detection 3. serial-to-parallel conversion 4. 8-bit parallel output internal clocking and control functions are transpar- ent to the user. details of data timing can be seen in figures 10 through 15. the S3037 supports clock recovery for the oc-12/ stm-4 or oc-3/stm-1 data rates. differential serial data is input to the chip at the specified rate and clock recovery is performed on the incoming data stream. a reference clock is required to minimize the pll lock time and provide a stable output clock source in the absence of serial input data. retimed data and clock are output from the S3037. amcc congo (s1201) pos/atm sonet mapper amcc nile (s1202) atm sonet mapper suggested interface devices
4 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c figure 4. input jitter tolerance specification f0 f1 f2 f3 ft 0.15 1.5 15 sinusodal input jitter amplitude (ui p-p) frequency oc/sts level f0 (hz) f2 (hz) f3 (khz) ft (khz) f1 (hz) 12 10 30 300 25 250 3 10 30 300 6.5 65 figure 5. jitter transfer specification fc p jitter transfer frequency acceptable range slope = -20 db/decade oc/sts level fc (khz) p (db) 12 1,2 500 0.1 3 1,2 130 0.1 1. bellcore specifications: tr-nwt-000253, issue 2, december 1991. 2. ccitt recommendations: g.958. table 2. jitter tolerance r e t e m a r a pn i mp y tx a ms t i n us n o i t i d n o c e c n a r e l o t r e t t i j 2 1 - s t s 4 . 05 6 . 0i uz h m 5 < f < z h k 0 5 2 5 . 14 i uz h k 5 2 < f < z h 0 0 3 5 10 2i uz h 0 3 < f < z h 0 1 e c n a r e l o t r e t t i j 3 - s t s 4 . 08 . 0i uz h m 3 . 1 < f < z h k 5 6 5 . 15 i uz h k 5 . 6 < f < z h 0 0 3 5 12 2i uz h 0 3 < f < z h 0 1
5 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c 1:8 serial to parallel timing gen clock and data recovery rstb rsdp/n frame byte detect dleb oof fp pout[7:0] 8 backup reference gen poclk 8 pin[7:0] 8:1 parallel to serial tsdp/n piclk timing gen pclk clock synthesizer rstb d mode 0 mode 1 txcap1 txcap2 transmitter receiver lleb slptime refclkp/n ttlref sdpecl testen rxcap1 rxcap2 0 1 1 0 1 0 rstb rstb rstb 1 0 1 0 0 1 0 1 figure 6. S3037 transceiver functional block diagram
6 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c S3037 transceiver functional description transmitter operation the S3037 transceiver chip performs the serializing stage in the processing of a transmit sonet sts-3 or sts-12 bit serial data stream. it converts the 8-bit parallel 19.44 or 77.76 mbits/sec data stream into bit serial format at 155.52 or 622.08 mbit/sec. a high-frequency bit clock can be generated from a 19.44 or 77.76 mhz frequency reference by using an integral frequency synthesizer consisting of a phase- locked loop circuit with a divider in the loop. diagnostic loopback is provided (transmitter to re- ceiver). see other operating modes. clock synthesizer the clock synthesizer, shown in the block diagram in figure 6, is a monolithic pll that generates the se- rial output clock phase synchronized with the input reference clock (refclkp/n or ttlref). the refclkp/n input must be generated from an lvpecl crystal oscillator which has a frequency ac- curacy that meets the values specified in table 9 in order for the tsd frequency to have the same accu- racy required for operation in a sonet system. lower accuracy crystal oscillators may be used in applications less demanding than sonet/sdh. ttlref must be at logic "one" if refclkp/n are used. for ttl reference operation, the ttlref input should be driven with an lvttl crystal oscillator output with the ppm accuracy specified in table 9 for sonet compliance. in this mode, refclkp should be connected to lvpecl "high" and refclkn should be tied to lvpecl "low." the on-chip pll consists of a phase detector, which compares the phase relationship between the vco out- put and the refclkp/n input, a loop filter which converts the phase detector output into a smooth dc voltage, and a vco, whose frequency is varied by this voltage. the loop filter generates a vco control voltage based on the average dc level of the phase discrimi- nator output pulses. the loop filters corner frequency is optimized to minimize output phase jitter. timing generation the timing generation function, seen in figure 6, provides a byte rate version of the transmit serial clock. this circuitry also provides an internally gen erated load signal, which transfers the pin[7:0] data from the parallel input register to the serial shift register. the pclk output is a byte rate version of transmit serial clock at 19.44 or 77.76 mhz. pclk is intended for use as a byte speed clock for upstream multiplex- ing and overhead processing circuits. using pclk for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3037 device. parallel-to-serial converter the parallel-to-serial converter shown in figure 6 is comprised of two byte-wide registers. the first regis- ter latches the data from the pin[7:0] bus on the rising edge of piclk. the second register is a paral- lel loadable shift register which takes its parallel input from the first register. the load signal, which latches the data from the par- allel to the serial shift register, has a fixed relationship to pclk. if piclk is tied to pclk, the pin[7:0] data latched into the parallel register will meet the timing specifications with respect to the load signal. if piclk is not tied to pclk, the delay must meet the timing requirements shown in figure 10. e d o m ] 0 : 1 [] 0 : 1 [ ] 0 : 1 [ ] 0 : 1 [] 0 : 1 [ k c o l c e c n e r e f e r y c n e u q e r fy c n e u q e r f y c n e u q e r f y c n e u q e r fy c n e u q e r f g n i t a r e p o e d o me d o m e d o m e d o me d o m 0 0z h m 4 4 . 9 12 1 - s t s 1 1z h m 6 7 . 7 72 1 - s t s 1 0z h m 4 4 . 9 13 - s t s 0 1z h m 6 7 . 7 73 - s t s table 3. reference frequency options table 4. reference jitter limits y c n e u q e r f d n a b e c n e r e f e r m u m i x a m r e t t i j k c o l c g n i t a r e p o e d o m z h m 5 o t z h k 2 1s m r s p 4 12 1 C s t s z h m 1 o t z h k 2 1s m r s p 6 53 C s t s
7 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c the loop filter transfer function is optimized to enable the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. this transfer function yields the typical capture time stated in table 9 for random incoming nrz data. a single external clean-up capacitor is utilized as part of the loop filter. the total loop dynamics of the clock recovery pll yield a jitter tolerance which exceeds the minimum tolerance proposed for sonet equipment by the bellcore tr-nwt-000253 standard, shown in figure 7. lock detect the S3037 contains a lock detect circuit which moni- tors the integrity of the serial data inputs. if the received serial data fails the frequency test, the pll will be forced to lock to the local reference clock. this will maintain the correct frequency of the poclk output under loss of signal or loss of lock conditions. if the recovered clock frequency deviates from the local reference clock frequency by more than the specified ppm, the pll will go out of lock. the lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. if the recov- ered clock frequency is determined to be within the specified ppm, the pll will go into lock. the asser- tion of sdpecl will also cause an out-of-lock condition. see table 9. backup reference generator the backup reference generator seen in figure 6 provides backup reference clock signals to the clock recovery block when the clock recovery block de- tects a loss of signal condition. it contains a counter that divides the clock output from the clock recovery block down to the same frequency as the reference clock. figure 7. clock recovery jitter tolerance 25k 65k 250k 6.5k 300 30 0.15 1.5 15 jitter frequency (hz) jitter amplitude (ul p-p) minimum proposed tolerance (tr-nwt-000253) oc-12 oc-3 receiver operation the S3037 transceiver chip provides the first stage of digital processing of a receive sonet sts-3 or sts-12 bit-serial stream. it converts the bit-serial 155.52 or 622.08 mbit/sec data stream into a 19.44 or 77.76 mbits 8-bit parallel data format. clock recovery is performed on the incoming scrambled nrz data stream. a 19.44 or 77.76 mhz reference clock is required for phase locked loop start-up and proper operation under loss of signal conditions. an integral prescaler and phase locked loop circuit are used to multiply this reference to the nominal bit rate. clock recovery clock recovery, as shown in the block diagram in figure 6, generates a clock that is at the same fre- quency as the incoming data bit rate at the rsd input or, in loopback, the transmitter data output. the clock is phase aligned by a pll so that it samples the data in the center of the data eye pattern. the phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. out- put pulses from the discriminator indicate the required direction of phase corrections. these pulses are smoothed by an integral loop filter. the output of the loop filter controls the frequency of the voltage controlled oscillator (vco), which gener- ates the recovered clock.
8 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c frame and byte boundary detection the frame and byte boundary detection circuitry searches the incoming data for three consecutive a1 bytes followed immediately by three consecutive a2 bytes. framing pattern detection is enabled and dis- abled by the out-of-frame (oof) input. detection is enabled by a rising edge on oof, and remains en- abled for the duration that oof is set high. it is disabled when a framing pattern is detected and oof is no longer set high. when framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming data stream (rsd or looped transmitter data). the timing generator block takes the located byte boundary and uses it to block the incoming data stream into bytes for output on the paral- lel output data bus (pout[7:0]). the frame boundary is reported on the frame pulse (fp) output when any 48-bit pattern matching the framing pattern is detected on the incoming data stream. when framing pattern detection is disabled, the byte boundary is frozen to the location found when detection was previously enabled. only framing patterns aligned to the fixed byte bound- ary are indicated on the fp output. the probability that random data in an sts-3 or sts- 12 stream will generate the 48-bit framing pattern is extremely small. it is highly improbable that a mimic pattern would occur within one frame of data. there- fore, the time to match the first frame pattern and to verify it with down-stream circuitry, at the next occur- rence of the pattern, is expected to be less than the required 250 m s, even for extremely high bit error rates. once down-stream overhead circuitry has verified that frame and byte synchronization are correct, the oof input can be set low to disable the frame search pro- cess from trying to synchronize to a mimic frame pattern. (see figures 12-14.) serial-to-parallel converter the serial-to-parallel converter consists of three 8-bit registers. the first is a serial-in, parallel-out shift regis- ter, which performs serial-to-parallel conversion clocked by the clock recovery block. the second is an 8-bit internal holding register, which transfers data from the serial-to-parallel register on byte boundaries as de- termined by the frame and byte boundary detection block. on the falling edge of the free running poclk, the data in the holding register is transferred to an out- put holding register which drives poutp/n[7:0]. the delay through the serial to parallel converter can vary from 1.5 to 2.5 byte periods (12 to 20 serial bit periods) measured from the first bit of an incoming byte to the beginning of the parallel output of that byte. the variation in the delay is dependent on the alignment of the internal parallel load timing, which is synchronized to the data byte boundaries, with respect to the falling edge of poclk, which is independent of the byte boundaries. the advantage of this serial-to-parallel converter is that poclk is neither truncated nor ex- tended during reframe sequences. other operating modes diagnostic loopback when the diagnostic loopback enable (dleb) input is active, a loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. the differential serial output data from the transmitter is routed to the clock recovery unit and serial-to-paral- lel block in place of the normal receive d ata stream (rsd). in diagnostic loopback mode the sdpecl input is ignored. line loopback when line loopback enable (lleb) is active, a loopback from the receiver to the transmitter at the serial data rate can be set up for facility loopback test- ing. the recovered clock is used to retime the incoming data before driving the tsdp/n outputs. in line loopback mode the sdpecl input is ignored. serial loop timing in serial loop timing (slptime) mode, the clock synthesizer pll of the S3037 is bypassed, and the timing of the entire transmitter section is controlled by the recovered receive serial clock. this mode is en- tered by using the slptime input. in this mode the refclkp/n, ttlref, and mode[1:0] inputs are ignored for all transmit functions. forward clocking for both 77.78 mhz and 19.44 mhz reference opera- tion, the S3037 operates in the forward clocking mode. the pll locks the pclk output of the transmitter section to the reference clock with a fixed and repeat- able phase relation ship. this allows the transmitter data source to also be the timing source for the serial clock synthesis. (see figure 15.)
9 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c table 5. S3037 transmitter pin assignment and descriptions (active high unless otherwise stated.) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 7 n i p 6 n i p 5 n i p 4 n i p 3 n i p 2 n i p 1 n i p 0 n i p l t t v li1 6 0 6 9 5 8 5 7 5 6 5 5 5 4 5 o t d e n g i l a , s / s t i b m 4 4 . 9 1 r o s / s t i b m 6 7 . 7 7 a . t u p n i a t a d l e l l a r a p t i b t n a c i f i n g i s t s o m e h t s i ] 7 [ n i p . k c o l c t u p n i l e l l a r a p k l c i p e h t t i b t s r i f e h t , d r o w m c p h c a e f o 1 t i b o t g n i d n o p s e r r o c ( o t g n i d n o p s e r r o c ( t i b t n a c i f i n g i s t s a e l e h t s i ] 0 [ n i p . ) d e t t i m s n a r t s i ] 0 : 7 [ n i p . ) d e t t i m s n a r t t i b t s a l e h t , d r o w m c p h c a e f o 8 t i b . k l c i p f o e g d e g n i s i r e h t n o d e l p m a s k l c i pl t t v li2 6y t u d % 0 5 y l l a n i m o n , z h m 4 4 . 9 1 r o 6 7 . 7 7 a . k c o l c t u p n i l e l l a r a p o t d e s u s i k l c i p . d e n g i l a s i ] 0 [ n i p h c i h w o t , k c o l c t u p n i e l c y c e h t n i r e t s i g e r g n i d l o h a o t n i s t u p n i n i p e h t n o a t a d e h t r e f s n a r t s e l p m a s k l c i p f o e g d e g n i s i r e h t . r e t r e v n o c l a i r e s - o t - l e l l a r a p . ] 0 : 7 [ n i p 1 p a c x t 2 p a c x t g o l a n ai0 1 9 d e t c e n n o c s i r o t i c a p a c r e t l i f p o o l x t e h t . r o t i c a p a c r e t l i f p o o l . 6 1 e r u g i f e e s . s n i p e s e h t o t p d s t n d s t . f f i d l c e p v l o5 1 6 1 m a e r t s a t a d l a i r e s l c e p v l l a i t n e r e f f i d . a t a d l a i r e s t i m s n a r t . e l u d o m r e t t i m s n a r t l a c i t p o n a o t d e t c e n n o c y l l a m r o n , s l a n g i s k l c pl t t v lo4 6e h t g n i d i v i d y b d e t a r e n e g k c o l c e c n e r e f e r a . k c o l c l e l l a r a p e t a n i d r o o c o t d e s u y l l a m r o n s i t i . t h g i e y b k c o l c t i b l a n r e t n i 7 3 0 3 s e h t d n a c i g o l m a e r t s p u n e e w t e b s r e f s n a r t e d i w - e t y b . e c i v e d
10 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c table 6. S3037 receiver pin assignment and descriptions (active high unless otherwise stated.) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p d s r n d s r . f f i d l c e p v l i5 2 6 2 n a o t d e t c e n n o c y l l a m r o n s l a n g i s m a e r t s . a t a d l a i r e s e v i e c e r n o s n o i t i s n a r t m o r f d e r e v o c e r s i k c o l c a . e l u d o m r e v i e c e r l a c i t p o . s t u p n i d s r e h t f o ol t t v li3 3n o i t c e t e d n r e t t a p g n i m a r f e l b a n e o t d e s u r o t a c i d n i e m a r f f o t u o s i c i g o l n o i t c e t e d n r e t t a p g n i m a r f e h t . 7 3 0 3 s e h t n i c i g o l l i t n u d e l b a n e s n i a m e r d n a , f o o n o e g d e g n i s i r a y b d e l b a n e r e v e h c i h w , w o l t e s s i f o o n e h w r o d e t c e t e d s i y r a d n u o b e m a r f e s l u p m u m i n i m a h t i w l a n g i s s u o n o r h c n y s a n a s i f o o . r e g n o l s i ) . 4 1 h g u o r h t 2 1 s e r u g i f e e s ( . d o i r e p k l c o p e n o f o h t d i w l c e p d sl c e p v li0 2a . h g i h e v i t c a . n w o d - l l u p l a n r e t n i h t i w l c e p v l . t c e t e d l a n g i s l a n r e t x e e h t y b n e v i r d e b o t t u p n i l c e p v l k 0 1 d e d n e - e l g n i s l a c i t p o d e v i e c e r f o s s o l a e t a c i d n i o t e l u d o m r e v i e c e r l a c i t p o n i a t a d l a i r e s e h t n o a t a d e h t , e v i t c a n i s i l c e p d s n e h w . r e w o p n e h w . o r e z t n a t s n o c a o t d e c r o f y l l a n r e t n i e b l l i w s n i p ) n / p d s r ( d e s s e c o r p e b l l i w s n i p n / p d s r e h t n o a t a d , e v i t c a s i l c e p d s . y l l a m r o n 1 p a c x r 2 p a c x r g o l a n ai1 3 2 3 s r o t s i s e r d n a r o t i c a p a c r e t l i f p o o l x r e h t . r o t i c a p a c r e t l i f p o o l . 7 1 e r u g i f e e s . s n i p e s e h t o t d e t c e n n o c e r a 7 t u o p 6 t u o p 5 t u o p 4 t u o p 3 t u o p 2 t u o p 1 t u o p 0 t u o p l t t v lo5 4 4 4 3 4 1 4 0 4 9 3 7 3 6 3 d e n g i l a , s / t i b m 4 4 . 9 1 r o s / t i b m 6 7 . 7 7 a . s u b t u p t u o a t a d l e l l a r a p t s o m e h t s i ] 7 [ t u o p . k c o l c t u p t u o l e l l a r a p k l c o p e h t o t t s r i f e h t , d r o w m c p h c a e f o 1 t i b o t g n i d n o p s e r r o c ( t i b t n a c i f i n g i s g n i d n o p s e r r o c ( t i b t n a c i f i n g i s t s a e l e h t s i ] 0 [ t u o p . ) d e v i e c e r t i b s i ] 0 : 7 [ t u o p . ) d e v i e c e r t i b t s a l e h t , d r o w m c p h c a e f o 8 t i b o t . k l c o p f o e g d e g n i l l a f e h t n o d e t a d p u p fl t t v lo5 3a t a d g n i m o c n i e h t n i s e i r a d n u o b e m a r f s e t a c i d n i . e s l u p e m a r f s a , d e l b a n e s i n o i t c e t e d n r e t t a p g n i m a r f f i . ) d s r ( m a e r t s k l c o p e n o r o f h g i h s e s l u p p f , t u p n i f o o e h t y b d e l l o r t n o c d e t c e t e d s i g n i m a r f e h t g n i h c t a m e c n e u q e s t i b - 8 4 a n e h w e l c y c , d e l b a s i d s i n o i t c e t e d n r e t t a p g n i m a r f n e h w . s t u p n i d s r e h t n o e t y b r e t f a , m a e r t s a t a d g n i m o c n i e h t n e h w h g i h s e s l u p p f e h t n o d e t a d p u s i p f . n r e t t a p g n i m a r f e h t s e h c t a m , t n e m n g i l a . k l c o p f o e g d e g n i l l a f k l c o pl t t v lo7 4% 0 5 y l l a n i m o n , z h m 4 4 . 9 1 r o 6 7 . 7 7 a . k c o l c t u p t u o l e l l a r a p ] 0 : 7 [ t u o p o t d e n g i l a s i t a h t k c o l c t u p t u o e t a r e t y b , e l c y c y t u d e h t n o d e t a d p u e r a p f d n a ] 0 : 7 [ t u o p . a t a d t u p t u o l a i r e s e t y b . k l c o p f o e g d e g n i l l a f
11 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c table 7. S3037 common pin assignment and descriptions (active high unless otherwise stated.) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d n e t s e tl t t v li0 5e h t s s a p y b o t h g i h t e s . h g i h e v i t c a . l a n g i s e l b a n e k c o l c t s e t . s t s e t n o i t c u d o r p g n i r u d l l p p k l c f e r n k l c f e r . f f i d l c e p v l i6 5 t i b l a n r e t n i e h t r o f e c n e r e f e r e h t s a d e s u . t u p n i k c o l c e c n e r e f e r a o t d e t c e n n o c e b t s u m p k l c f e r . r e z i s e h t n y s y c n e u q e r f k c o l c . d e s u s i f e r l t t f i e t a t s o r e z c i g o l a o t n k l c f e r d n a e n o c i g o l f e r l t tl t t v li4 e c n e r e f e r e h t s a d e s u e b n a c t a h t t u p n i k c o l c e c n e r e f e r l t t d e i t e b t s u m ( . r e z i s e h t n y s y c n e u q e r f k c o l c t i b l a n r e t n i e h t r o f . ) d e s u s i n / p k l c f e r f i h g i h b e l dl t t v li8 1c i t s o n g a i d s t c e l e s . w o l e v i t c a . e l b a n e k c a b p o o l c i t s o n g a i d e h t s e s u e c i v e d 7 3 0 3 s e h t , h g i h s i b e l d n e h w . k c a b p o o l s e s u e c i v e d 7 3 0 3 s e h t , w o l n e h w . s t u p n i ) d s r ( a t a d y r a m i r p . r e t t i m s n a r t e h t m o r f a t a d k c a b p o o l c i t s o n g a i d e h t b t s rl t t v li9 1s e z i l a i t i n i . w o l e v i t c a . e c i v e d e h t r o f t u p n i t e s e r . t e s e r r e t s a m r o f h g i h e i t . g n i t s e t n o i t c u d o r p r o f e t a t s n w o n k a o t e c i v e d e h t . n o i t a r e p o l a m r o n b e l ll t t v li3 1n e h w . k c a b p o o l e n i l s t c e l e s . w o l e v i t c a . e l b a n e k c a b p o o l e n i l m o r f a t a d l a i r e s d e m i t e r e h t e t u o r l l i w 7 3 0 3 s e h t , w o l s i b e l l . s t u p t u o r e t t i m s n a r t e h t o t n o i t c e s e v i e c e r e h t 1 e d o m 0 e d o m l t t v li1 5 2 5 e c n e r e f e r e h t t c e l e s o t d e s u . s t u p n i t c e l e s e d o m g n i t a r e p o o s l a . ) 3 e l b a t e e s ( d e e p s g n i t a r e p o e h t d n a y c n e u q e r f k c o l c . t s e t r o f d e s u e m i t p l sl t t v li3 5o t d e s u . h g i h e v i t c a . t u p n i t c e l e s e m i t p o o l k c o l c l a i r e s d e s u e b o t n o i t c e s e v i e c e r e h t m o r f k c o l c d e r e v o c e r e h t e l b a n e . k c o l c t i m s n a r t d e z i s e h t n y s e h t f o e c a l p n i
12 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c table 8. S3037 power and ground pin assignments e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 1 , 0 c c v a x rv 3 . 31 2 4 2 y l p p u s r e w o p 1 , 0 d n g a x rd n g2 2 3 2 ) v 0 ( d n u o r g d n g k l c s rd n g7 2) v 0 ( d n u o r g c c v k l c s rv 3 . 38 2y l p p u s r e w o p c c v e r o c x rv 3 . 39 2y l p p u s r e w o p d n g e r o c x rd n g0 3) v 0 ( d n u o r g d n g l t td n g4 3 2 4 ) v 0 ( d n u o r g d n g n i l t td n g9 4) v 0 ( d n u o r g c c v l t tv 3 . 38 3 6 4 y l p p u s r e w o p c c v n i l t tv 3 . 38 4y l p p u s r e w o p c c v k l c pv 3 . 33 6y l p p u s r e w o p d n g k l c pd n g1) v 0 ( d n u o r g c c v e r o c x tv 3 . 33y l p p u s r e w o p d n g e r o c x td n g2) v 0 ( d n u o r g 1 , 0 d n g ad n g1 1 8 ) v 0 ( d n u o r g 1 , 0 c c v av 3 . 32 1 7 y l p p u s r e w o p c c v t u o x tv 3 . 34 1y l p p u s r e w o p d n g t u o x td n g7 1) v 0 ( d n u o r g
13 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c figure 8. 64 pqfp package e c i v e dr e w o p x a m q a j 7 3 0 3 sw 1 2 . 1w / c ? 5 4 thermal management top view
14 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c 1 2 3 4 5 6 7 8 9 10 11 19 20 21 22 23 24 25 26 27 28 29 62 61 60 59 58 57 56 55 54 53 52 48 47 46 45 44 43 42 41 40 39 38 S3037 pinout (64 pqfp) 37 36 ttlinvcc poclk ttlvcc pout7 pout6 pout5 ttlgnd pout4 pout3 pout2 ttlvcc pout1 35 34 33 pout0 fp ttlgnd 17 18 rstb sdpecl rxavcc0 rxagnd0 rxagnd1 rxavcc1 rsdp rsdn rsclkgnd rsclkvcc rxcorevcc txoutgnd dleb 30 31 32 rxcoregnd rxcap1 rxcap2 64 63 pclkvcc piclk pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 slptime pclk 51 50 49 mode0 mode1 testen 12 13 pclkgnd txcoregnd txcorevcc ttlref refclkn refclkp avcc1 agnd1 txcap2 txcap1 agnd0 avcc0 14 15 16 lleb tsdn top view txoutvcc tsdp ttlingnd oof figure 9. pinout assignments
15 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c table 9. performance specifications r e t e m a r a pn i mp y tx a ms t i n us n o i t i d n o c o c v l a n i m o n y c n e u q e r f r e t n e c 8 0 . 2 2 6z h m r e t t i j t u p t u o a t a d 2 1 - s t s k l c f e r z h m 4 4 . 9 1 - k l c f e r z h m 6 7 . 7 7 - 3 - s t s k l c f e r z h m 4 4 . 9 1 - k l c f e r z h m 6 7 . 7 7 - 7 0 0 . 0 4 0 0 . 0 3 0 0 . 0 2 0 0 . 0 ) s m r ( i u k c o l n i , r e t t i j s m r k c o l c e c n e r e f e r e c n a r e l o t y c n e u q e r f 0 2 -0 2 +m p p t u p t u o t e n o s t e e m o t d e r i u q e r n o i t a c i f i c e p s y c n e u q e r f d n a 3 - s t s / 3 - c o 2 1 - s t s / 2 1 - c o e g n a r e r u t p a c e g n a r k c o l e m i t e r u t p a c 0 0 2 % 2 1 2 3 m p p s e c n e r e f e r d e x i f o t t c e p s e r h t i w y c n e u q e r f e m i t k c o l n o i t i s i u q c a 6 1s % 0 2 f o y t i s n e d n o i t i s n a r t m u m i n i m d n a p u d e r e w o p y d a e r l a e c i v e d h t i w k c o l c e c n e r e f e r d i l a v k c o l c e c n e r e f e r e l c y c y t u d t u p n i0 40 6i u f o % & e s i r k c o l c e c n e r e f e r s e m i t l l a f 0 . 2s n e d u t i l p m a f o % 0 8 o t % 0 2 & e s i r t u p t u o l c e p v l s e m i t l l a f 0 5 4s p 0 5 , % 0 8 o t % 0 2 w p a c f p 5 , d a o l t a e c n e r e f f i d y c n e u q e r f f o t u o s e o g l l p h c i h w k l c f e r ( k c o l d e d i v i d e h t o t d e r a p m o c . ) k c o l c o c v n w o d 0 4 30 1 62 3 7m p p . k c o l n i y l s u o i v e r p t a e c n e r e f f i d y c n e u q e r f s e o g l l p e v i e c e r h c i h w k l c f e r ( k c o l o t n i d e d i v i d e h t o t d e r a p m o c . ) k c o l c o c v n w o d 4 4 25 0 36 6 3m p p . k c o l f o t u o y l s u o i v e r p 2 1 - s t s / 2 1 - c o e c n a r e l o t r e t t i j 4 . 0i u n o e d u t i l p m a . r e t t i j t u p n i l a d i o s u n i s 0 5 2 m o r f s t u p n i a t a d n / p i t a d r e s . z h m 5 o t z h k
16 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c table 11. recommended operating conditions table 12. lvttl input/output dc characteristics table 10. absolute maximum ratings r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? v n o e g a t l o v c c d n g o t t c e p s e r h t i w5 . 0 -0 . 5 +v n i p t u p n i l t t v l y n a n o e g a t l o v5 . 0 -5 . 5 +v n i p t u p n i l c e p v l y n a n o e g a t l o v0v c c v t n e r r u c k n i s t u p t u o l t t v l8a m t n e r r u c e c r u o s t u p t u o l t t v l8a m t n e r r u c e c r u o s t u p t u o l c e p v l d e e p s h g i h0 5a m r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a00 7c ? v n o e g a t l o v c c d n g o t t c e p s e r h t i w n o i t a r e p o v 3 . 3 5 3 1 . 33 . 35 6 4 . 3v n i p t u p n i l t t v l y n a n o e g a t l o v05 . 5v n i p t u p n i l c e p v l y n a n o e g a t l o v c c v v 2 - c c vv t n e r r u c y l p p u s c c i0 5 3a m n o i t a p i s s i d r e w o p d p1 2 . 1w esd ratings the S3037 is rated to the following esd voltages based on the human body model: 1. all pins are rated at or above 1000 v except pin1, pin10, pin31, and pin32. r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v h o ) l t t ( e g a t l o v h g i h t u p t u o 1 . 2 2 . 2 v v v c c i , n i m = h o a m 4 . 2 - = v c c i , n i m = h o a m 1 . 0 - = v l o ) l t t ( e g a t l o v w o l t u p t u o5 . 0vv c c i , n i m = l o a m 4 . 2 = v h i ) l t t ( e g a t l o v h g i h t u p n i0 . 2 l t t v c c v i h v t a a m 1 @ h i v 5 . 5 = v l i ) l t t ( e g a t l o v w o l t u p n i08 . 0v i h i ) l t t ( t n e r r u c h g i h t u p n i0 2a v n i v 4 . 2 = i l i ) l t t ( t n e r r u c w o l t u p n i0 0 5 Ca v n i v 5 . 0 =
17 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v l i e g a t l o v w o l t u p n i v c c 0 0 0 . 2 C v c c 1 4 4 . 1 C v w o l t u p n i d e e t n a r a u g d e d n e - e l g n i s r o f e g a t l o v s t u p n i v h i e g a t l o v h g i h t u p n i v c c 5 2 2 . 1 C v c c 0 7 5 . 0 C v h g i h t u p n i d e e t n a r a u g d e d n e - e l g n i s r o f e g a t l o v s t u p n i v l i e g a t l o v w o l t u p n i v c c 0 0 0 . 2 C v c c 0 0 7 . 0 C v w o l t u p n i d e e t n a r a u g l a i t n e r e f f i d r o f e g a t l o v s t u p n i v h i e g a t l o v h g i h t u p n i v c c 0 5 7 . 1 C v c c 0 5 4 . 0 C v h g i h t u p n i d e e t n a r a u g l a i t n e r e f f i d r o f e g a t l o v s t u p n i v d i e g a t l o v l a i t n e r e f f i d t u p n i0 0 2 . 00 0 5 . 00 0 4 . 1v e g a t l o v t u p n i l a i t n e r e f f i d i d h i t n e r r u c h g i h t u p n i l a i t n e r e f f i d0 0 5 . 0 C0 0 0 . 0 2a v d i v m 0 0 5 = i d l i t n e r r u c w o l t u p n i l a i t n e r e f f i d0 0 5 . 0 C0 0 0 . 0 2a v d i v m 0 0 5 = i h i t n e r r u c h g i h t u p n i d e d n e e l g n i s0 0 1a l a n r e t n i s a h t u p n i d s d a o l v 8 . 1 o t k 4 2 r o t s i s e r i l i t n e r r u c w o l t u p n i d e d n e e l g n i s0 0 1 Ca l a n r e t n i s a h t u p n i d s d a o l v 8 . 1 o t k 4 2 r o t s i s e r v l o e g a t l o v w o l t u p t u o 1 v c c 0 0 0 . 2 C v c c 0 0 5 . 1 C v 0 5 w o t n o i t a n i m r e t v c c v 2 C v h o e g a t l o v h g i h t u p t u o 1 v c c 0 1 1 . 1 C v c c 0 7 6 . 0 C v 0 5 w o t n o i t a n i m r e t v c c v 2 C v d o e g a t l o v l a i t n e r e f f i d t u p t u o0 0 8 . 06 6 . 2v 0 5 w o t n o i t a n i m r e t v c c v 2 C v e l g n i s o e g a t l o v d e d n e e l g n i s t u p t u o0 0 4 . 00 3 3 . 1v 0 5 w o t n o i t a n i m r e t v c c v 2 C table 13. lvpecl input/output dc characteristics 1. output macros are 10k pecl equivalent.
18 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n u d t k l c i p k l c p m o r f y a l e d k l c i p05 . 5s n s t n i p k l c i p . t . r . w e m i t p u t e s ] 0 : 7 [ n i p5 . 1s n h t n i p k l c i p . t . r . w e m i t d l o h ] 0 : 7 [ n i p0 . 1s n table 14. transmitter ac timing characteristics table 15. receiver ac timing characteristics r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n u e l c y c y t u d k l c o p0 40 6% p t t u o p 3 - s t s @ y a l e d . p o r p d i l a v ] 0 : 7 [ t u o p o t w o l k l c o p 2 1 - s t s @ y a l e d . p o r p d i l a v ] 0 : 7 [ t u o p o t w o l k l c o p 8 - 3 - 0 1 s n s n s t t u o p k l c o p . t . r . w e m i t p u t e s p f d n a ] 0 : 7 [ t u o p 1 4s n h t t u o p k l c o p . t . r . w e m i t d l o h p f d n a ] 0 : 7 [ t u o p 1 3s n 1. setup and hold times are specified for an interface which directly connects the S3037 receiver parallel outputs to the data a nd clock inputs on an external register.
19 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c figure 10. pin ac input timing ts pin td piclk th pin piclk pclk pin[7:0] 1. when a setup time is specified on lvttl signals between an input and a clock, the setup time is the time in nanoseconds from the 50% crossover point of the input to the 50% crossover point of the clock. 2. when a hold time is specified on lvttl signals between an input and a clock, the hold time is the time in nanoseconds from the 50% crossover point of the clock to the 50% crossover point of the input. figure 11. receiver output timing diagram pout[7:0]fp poclk th pout tp pout tp pout 50% ts pout th pout duty cycle min duty cycle max tp pout 70% max min min 30% notes on output timing: 1. output propagation delay time of lvttl outputs is the time in nanoseconds from the 50% crossover point of the reference signal to the 30% or 70% point of the output. 2. maximum output propagation delays of lvttl outputs are measured with a 15 pf load on the outputs.
20 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c receiver framing figure 12 shows a typical reframe sequence in which a byte realignment is made. the frame and byte boundary detection is enabled by the rising edge of oof and remains enabled while oof is high. both boundaries are recognized upon receipt of the third a2 byte which is the first data byte to be reported with the correct byte alignment on the outgoing data bus (pout[7:0]). concurrently, the frame pulse is set high for one poclk cycle. when interfacing with a section terminating device, the oof input remains high for one full frame after the first frame pulse while the section terminating device verifies internally that the frame and byte alignment are correct, as shown in figure 13. since at least one framing pattern has been detected since the rising edge of oof, boundary detection is dis- abled when oof is set low. the frame and byte boundary detection block is acti- vated by the rising edge of oof, and stays active until the first fp pulse or until oof goes low, which- ever occurs last. figure 12 shows a typical oof timing pattern which occurs when the S3037 is con- nected to a down stream section terminating device. oof remains high for one full frame after the first fp pulse. the frame and byte boundary detection block is active until oof goes low. figure 14 shows the frame and byte boundary detec- tion activation by a rising edge of oof, and deactivated by the first fp pulse. figure 12. frame and byte boundary detection 1. range of input to output delay can be 1.5 to 2.5 poclk cycles. figure 13. oof operation timing boundary detection enabled oof fp oof fp boundary detection enabled figure 14. alternate oof timing a1 a1 a1 a2 a2 a2 a2 a2 note 1 a1 a1 a1 a2 a2 a2 (28h) invalid data valid data recovered clock/ refclk oof serdati pout[7:0] poclk fp
21 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c S3037 with data clock synchronous to reference clock in some applications it is necessary to "forward clock" the data in a sonet/sdh system. in this ap- plication the reference clock from which the high speed serial clock is synthesized and the parallel data clock both originate from the same (usually ttl/cmos) clock source. this application note ex- plains how the amcc S3037 can be configured to operate in this mode. clock control logic description the timing control logic in the S3037 automatically generates an internal load signal which has a fixed relationship to the reference clock. the logic takes into account the variation of the reference clock to the internal load signal over temperature and voltage. the connections required to implement the design are shown in figure 15. the setup and hold times for the piclk to the data must be met by the controller asic. it is recommended that latching the data on the falling edge of the output reference clock be latched in order to meet the required specifications. possible problems in order to meet the jitter generation specifications required by sonet, the jitter of the reference clock must be minimized. it may be difficult to meet the sonet jitter generation specifications using a refer- ence clock input with a ttl reference source. power sequencing when the S3037 is operated with a 5 volt controller such as the pmc5355 suni, it is recommended that power be applied to the S3037 before or simulta- neously (time difference less than 1 ms) with the application of power to the 5 volt controller. if this condition cannot be met, series resistance of at least 33 w is required on all ttl inputs driven from the 5 volt environment. please note that 33 w is already recommended on dynamically switching input signals such as pin[7:0], oof, piclk, and ttl ref to limit overshoot and ringing. static control lines such as lleb, dleb, slptime, mode[1:0], and rstb should also be provided with series resistors of at least 33 w (100 ohms recommended) to limit input current if the 5 volt environment is powered while the 3.3 volt vcc of the S3037 is off. application note
22 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c asic data pin[7:0] piclk serial data S3037 8 output reference clock output data input reference clock figure 15. S3037 with data clocked by reference clock txcap1 0.01 f txcap2 S3037 figure 16. transmitter loop filter capacitor connections figure 17. receiver loop filter capacitor connections rxcap1 100 2.2 f rxcap2 100 S3037
23 S3037 sonet/sdh/atm oc-3/12 transceiver w/cdr december 10, 1999 / revision c ordering information x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i C s7 3 0 3p f q p 4 6 C f q x xxxx xx prefix device package amcc is a registered trademark of applied micro circuits corporation. copyright ? 1999 applied micro circuits corporation amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1

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